1. Field of the Invention
The present invention relates to a method and apparatus for detecting (deriving)/storing a maximum and/or minimum value (peak value) of an input signal waveform suitable for use with a display device such as an oscilloscope.
2. Description of the Related Art
Oscilloscopes have been used for monitoring waveforms of various data, among other purposes. They are essential and useful for research and developments, manufacturing, and the like of electronic devices, but they have had one significant disadvantage in that they are unable to store signal waveforms. With the progress of digital technology, digital oscilloscopes have been developed allowing them to store signal waveforms. A waveform storing circuit digitally processes various types of analog input signals and stores processed digital data. A combination of a waveform storing circuit and a display, a computer, or the like allows stored waveforms to be observed or to be applied to other applications.
An analog input signal is sampled at high speed, and A/D converted into digital data. Maximum peak amplitudes (or maximum and minimum values) of the digital data in an optional time period are sequentially stored and displayed. In this manner, very high speed noises which are called glitches and are impossible to be detected by general sampling technology can be detected, envelopes can be measured, and aliasing can be detected. It is well known that peak values can be detected by detecting maximum or minimum values in a similar manner.
FIG. 1 is a block diagram of a circuit for detecting/storing a peak value of a waveform according to a related art. In this circuit, an analog input waveform signal is converted into digital data by an A/D converter. A maximum or minimum value detecting unit (hereinafter called a peak value detecting unit) detects a maximum or minimum value (hereinafter called a peak value) of the digital data and stores the peak value in a memory. In FIG. 1, only one of the maximum and minimum value detecting units is shown. In the following description, a maximum value detecting unit is used as a representative of the peak value detecting unit, and a maximum value is derived as the peak value. It is obvious that the same technology is applicable to detecting a minimum value.
Referring to FIG. 1, an analog input waveform signal is applied to an input terminal 50. The analog input waveform signal applied to the peak value detecting/storing circuit is sampled, and the sampled value is converted into digital data at a timing of a first clock signal 57 by an A/D converter 51. A comparator 52 compares a digital data input A (supplied from the A/D converter 51) with a digital data input B (supplied from a latch 54). An OR gate 53 outputs a signal (an enable signal for the latch 54) in accordance with a digital output signal from the comparator 52 and a second clock signal 58. The latch 54 latches the digital data signal from the A/D converter 51 at a timing of the first clock signal 57. A memory 55 stores a maximum value of digital data from the latch 54 at a timing of the second clock signal 58. The maximum value is output from an output terminal 56 of the peak value detecting/storing circuit.
In the circuit structure described above, the comparator 52, OR gate 53, and latch 54 constitute a maximum value detecting unit 59 (as described earlier, only one detecting unit is shown in FIG. 1. Both the maximum and minimum value detecting units are required for detecting and storing the maximum and minimum values).
Next, the operation of the peak value detecting/storing circuit according to the related art will be described. Referring to FIG. 1, an analog input waveform signal applied to the signal input terminal 50 of the circuit is supplied to the A/D converter 51 and converted into n-bit digital data at a timing of the first clock signal 57. The n-bit digital data is supplied to the latch circuit 54 and comparator 52 at its input A of the maximum value detecting unit 59.
The comparator 52 is supplied with the n-bit digital data from the A/D converter 51 at its input A and with n-bit digital data latched by the latch 54 at its other input B. Both n-bit digital data are compared by the comparator 52.
In the maximum value detecting unit 59, of the comparison results A&gt;B and A&lt;B, the comparator 52 outputs a signal to the OR gate 53 when the comparison result is A&gt;B (if both the maximum and minimum values are to be detected, the maximum and minimum value detecting units are used, and one comparator supplies its output when the comparison result is A&gt;B whereas the other comparator outputs a signal when the comparison result is A&lt;B).
The OR gate 53 is supplied with an output from the comparator 52 and the second clock signal 58, and outputs an enable signal to the latch 54 at the timing of either an output from the comparator 53 for A&gt;B or the second clock signal 58.
The latch 54 enabled by the enable signal supplied from the OR gate 53 latches the data from the A/D converter 51 and outputs the data at a timing of the first clock signal 57.
The memory 55 stores the digital data at a timing of the second clock signal 58, and the maximum value of digital data is output from the signal output terminal 56 when necessary.
A peak value detecting/storing circuit having the structure described above is shown, for example, in JP-A-58-47661, and a comparator having the structure described above is shown, for example, in JP-A-3-62123.
In the circuit for detecting/storing a waveform peak value according to the related art, however, n-bit digital data is fed back from the latch 54 to the comparator 52. This feedback delay time t.sub.PD adversely affects a peak value detecting speed. The delay time t.sub.PD depends on the operation speeds of these devices including the comparator and latch. Therefore, there is a limit in improving the peak value detecting speed. In order to improve the peak value detecting speed, it becomes necessary to use expensive high speed devices. If the number of data bits increases, the number of comparison data bits increases, inevitably increasing the delay time t.sub.PD.
Even if high speed devices are used to speed up the peak value detecting operation (increasing the comparison speed), there is a limit to the read/write speed of the memory for storing a detected peak value, hindering an increase speed of the peak of value detecting operation. The operation speed of a memory is slower than an A/D conversion speed of an A/D converter, hindering an increase speed of the peak of value detecting operation.
A digital oscilloscope with expected high speed sampling and high resolution uses a combination of a circuit for detecting/storing a waveform peak value and a display. With a circuit for detecting/storing a waveform peak value of a related art, however, the operation speed of a peak value detecting unit is slow and therefore a high speed circuit has been long desired.